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Espressif Systems /ESP32 /SPI0 /PIN

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Interpret as PIN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CS0_DIS)CS0_DIS 0 (CS1_DIS)CS1_DIS 0 (CS2_DIS)CS2_DIS 0 (CK_DIS)CK_DIS 0MASTER_CS_POL 0MASTER_CK_SEL 0 (CK_IDLE_EDGE)CK_IDLE_EDGE 0 (CS_KEEP_ACTIVE)CS_KEEP_ACTIVE

Fields

CS0_DIS

SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin
CS1_DIS

SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin
CS2_DIS

SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin
CK_DIS

1: spi clk out disable 0: spi clk out enable
MASTER_CS_POL

In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.
MASTER_CK_SEL

In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.
CK_IDLE_EDGE

1: spi clk line is high when idle 0: spi clk line is low when idle
CS_KEEP_ACTIVE

spi cs line keep low when the bit is set.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data